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DS34T101 - (DS34T101 - DS34T108) Single/Dual/Quad/Octal TDM-Over-Packet Chip

General Description

The IETF PWE SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be transported transparently through a switched IP or MPLS packet network.

Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications.

Key Features

  • Full-Featured T1/E1/J1 LIU/Framer/TDM-OverPacket Supports Adaptive Clock Recovery, Common Clock (Using RTP), External Clock, and Loopback Timing Modes Selectable 32-Bit or 16-Bit Processor Bus Clock Rate Adapter for T1/E1 Master Clock 10/100 Ethernet MAC That Supports MII/RMII/SSMII Fully Compatible with IEEE 802.3 Standard VLAN Support A.

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Other Datasheets by Maxim Integrated (Analog Devices)

Part Number Description
DS34T102 (DS34T101 - DS34T108) Single/Dual/Quad/Octal TDM-Over-Packet Chip
DS34T104 (DS34T101 - DS34T108) Single/Dual/Quad/Octal TDM-Over-Packet Chip
DS34T108 (DS34T101 - DS34T108) Single/Dual/Quad/Octal TDM-Over-Packet Chip
DS34S101 (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34S102 (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip

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www.DataSheet4U.com Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be transported transparently through a switched IP or MPLS packet network. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. This eliminates the need for remote timing sources in cabinets and pedestals. The Ethernet side of the DS34T108 provides high QoS capabilities to its MII/RMII/SSMII port, while the WAN side supports full-featured T1/E1 framers and LIUs.