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MAX9426 - (MAX9424 - MAX9427) Lowest Jitter Quad PECL-to-ECL Differential Translators

This page provides the datasheet information for the MAX9426, a member of the MAX9424 (MAX9424 - MAX9427) Lowest Jitter Quad PECL-to-ECL Differential Translators family.

Description

The MAX9424

MAX9427 high-speed, low-skew quad PECL-to-ECL translators are designed for high-speed data and clock driver applications.

These devices feature an ultra-low 0.24ps(RMS) random jitter and channel-tochannel skew is less than 90ps in asynchronous mode.

Features

  • MAX9424.
  • MAX9427 Ordering Information INPUT OUTPUT (IN_, (OUT_, OUT_) IN_) MAX9424EHJ -40°C to +85°C 32 TQFP Open Open MAX9424EGJ.
  • -40°C to +85°C 32 QFN Open Open MAX9425EHJ -40°C to +85°C 32 TQFP Open 50Ω MAX9425EGJ.
  • -40°C to +85°C 32 QFN Open 50Ω MAX9426EHJ -40°C to +85°C 32 TQFP 100Ω Open MAX9426EGJ.
  • -40°C to +85°C 32 QFN 100Ω Open MAX9427EHJ -40°C to +85°C 32 TQFP 100Ω 50Ω MAX9427EGJ.
  • -40°C to +85°C 32 QFN 100Ω 50Ω.
  • Future product.
  • contact factory for avai.

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Other Datasheets by Maxim Integrated Products
  • MAX9420 - (MAX9420 - MAX9423) Quad Differential LVECL-to-LVPECL Translators
  • MAX9421 - (MAX9420 - MAX9423) Quad Differential LVECL-to-LVPECL Translators
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  • MAX9423 - (MAX9420 - MAX9423) Quad Differential LVECL-to-LVPECL Translators
  • MAX9424 - (MAX9424 - MAX9427) Lowest Jitter Quad PECL-to-ECL Differential Translators
  • MAX9425 - (MAX9424 - MAX9427) Lowest Jitter Quad PECL-to-ECL Differential Translators
  • MAX9427 - (MAX9424 - MAX9427) Lowest Jitter Quad PECL-to-ECL Differential Translators
  • MAX9450 - High-Precision Clock Generators

Full PDF Text Transcription

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www.DataSheet4U.com 19-2390; Rev 0; 4/02 Lowest Jitter Quad PECL-to-ECL Differential Translators General Description The MAX9424–MAX9427 high-speed, low-skew quad PECL-to-ECL translators are designed for high-speed data and clock driver applications. These devices feature an ultra-low 0.24ps(RMS) random jitter and channel-tochannel skew is less than 90ps in asynchronous mode. The four channels can be operated synchronously with an external clock, or in asynchronous mode determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. The parts differ from one another by their input and output termination options. The input options are an open input or an internal differential 100Ω termination.
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