s 700MHz min. shift frequency s Extended 100E VEE range of
–4.2V to
–5.5V s 9 bits wide for byte-parity applications s Asynchronous Master.
s Asynchronous Master Reset s Dual clocks s Fully compatible with industry standard 10KH,
100K ECL levels s Internal 75K.
The SY10/100E142 are high-speed 9-bit shift registers designed for use in new, high-performance ECL systems. The E142 can accept serial or parallel data to be shifted out in one direction as both serial and parallel outputs. The nine inputs, D0-D8, a.
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