LAN91C111 Key Features
- Optional Configuration via Serial EEPROM Inter
- Supports 8, 16 and 32 Bit CPU Accesses
- Internal 32 Bit Wide Data Path (Into Packet Buffer
- Built-in Transparent Arbitration for Slave Sequen
- Flat MMU Architecture with Symmetric Transmit
- 3.3V Operation with 5V Tolerant IO Buffers (See
- Single 25 MHz Reference Clock for Both PHY and
- External 25Mhz-output pin for an external PHY
- Low Power CMOS Design
- Supports Multiple Embedded Processor Host
