SAMA5D28 Datasheet | Microchip Technology

Features - Arm Cortex-A5 Core - Armv7-A architecture - Arm Trust Zone - NEON™ Media Processing Engine - Up to 500 MHz - ETM/ETB 8 Kbytes - Memory Architecture - Memory Management Unit (MMU) - 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache - 128-Kbyte L2 cache configurable to be used as an internal SRAM - One 128-Kbyte scrambled internal SRAM - One 160-Kbyte internal ROM - 64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader - 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table - High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting up to 512 Mbytes 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off only) / LPDDR1/ LPDDR2/LPDDR3, including “on-the-fly” encryption/decryption path - 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC) - System Running up to 166 MHz in Typical Conditions - Reset Controller (RSTC), Shutdown Controller (SHDWC), Periodic Interval Timer (PIT), independent Watchdog Timer (WDT) and secure Real-Time Clock (RTC) with clock calibration - One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for high-speed USB - Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz) - Internal low-power 12 MHz RC and 32 k Hz typical RC - Selectable 32.768 Hz low-power oscillator and 8 to 24 MHz oscillator - 51 DMA channels including two 16-channel 64-bit Central DMA Controllers © 2022 Microchip Technology Inc. and its subsidiaries plete Data Sheet DS60001476J-page 1 SAMA5D2 Series - 64-bit Advanced Interrupt Controller (AIC) - 64-bit Secure Advanced Interrupt Controller (SAIC) - Three programmable external clock signals - Low-Power Modes - Ultra-low-power mode with fast wake-up capability - Low-power Backup mode with 5-Kbyte SRAM and asynchronous partial wake-up features - Wake up from up to nine wake-up pins, UART reception, analog parison - Fast wake-up capability - Extended Backup mode with DDR in Self-Refresh...