Download SY100EP195V Datasheet PDF
SY100EP195V page 2
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SY100EP195V Key Features

  • Pin-for-Pin, Plug-In patible to the ON Semiconductor MC100EP195
  • Maximum Frequency >1.6 GHz
  • Programmable Range: 2.1 ns to 10.8 ns
  • 10 ps Increments
  • Open Input Default State
  • Safety Clamp on Inputs
  • D[0:10] Can Accept Either ECL, CMOS, or TTL
  • VBB Output Reference Voltage
  • Available in a 32-Pin TQFP Package

SY100EP195V Description

The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.1 ns to about 10.8 ns. The input can be PECL, LVPECL, NECL, or LVNECL.