dsPIC33EP64GS502 Overview
- Supports programming while operating - Supports partition soft swap Core: 16-Bit dsPIC33E CPU Code-Efficient (C and Assembly) Architecture Two 40-Bit Wide Accumulators Single-Cycle (MAC/MPY) with Dual Data Fetch Single-Cycle Mixed-Sign MUL Plus Hardware Divide 32-Bit Multiply Support Two Additional Working Register Sets (reduces context switching) Clock Management ±0.9% Internal Oscillator Programmable PLLs and...
dsPIC33EP64GS502 Key Features
- High-Speed ADC module
- 12-bit with 4 dedicated SAR ADC cores and one shared SAR ADC core
- Configurable resolution (up to 12-bit) for each ADC core
- Up to 3.25 Msps conversion rate per channel at 12-bit resolution
- 12 to 22 single-ended inputs
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Two digital parators
- Two oversampling filters for increased resolution
- Four Rail-to-Rail parators with Hysteresis
dsPIC33EP64GS502 Applications
- 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
- 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
- Dual Partition Flash Program Memory with Live Update (64-Kbyte devices)
- Supports programming while operating
- Supports partition soft swap