dsPIC33EP64GS502 - 16-Bit Digital Signal Controllers
Microchip Technology
Download the dsPIC33EP64GS502 datasheet PDF.
This datasheet also covers the dsPIC33EP16GS502 variant, as both devices belong to the same 16-bit digital signal controllers family and are provided as variant models within a single manufacturer datasheet.
Key Features
High-Speed ADC module: - 12-bit with 4 dedicated SAR ADC cores and one shared SAR ADC core - Configurable resolution (up to 12-bit) for each ADC core - Up to 3.25 Msps conversion rate per channel at 12-bit resolution - 12 to 22 single-ended inputs - Dedicated result buffer for each analog channel - Flexible and independent ADC trigger sources - Two digital comparators - Two oversampling filters for increased resolution.
Four Rail-to-Rail Comparators with Hysteresis: - Dedicate.
Full PDF Text Transcription for dsPIC33EP64GS502 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
dsPIC33EP64GS502. For precise diagrams, and layout, please refer to the original PDF.
dsPIC33EPXXGS50X FAMILY 16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators Operating Conditions...
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onnected High-Speed PWM, ADC, PGA and Comparators Operating Conditions • 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS Flash Architecture • Dual Partition Flash Program Memory with Live Update (64-Kbyte devices): - Supports programming while operating - Supports partition soft swap Core: 16-Bit dsPIC33E CPU • Code-Efficient (C and Assembly) Architecture • Two 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle Mixed-Sign MUL Plus Hardware Divide • 32-Bit Multiply Support • Two Additional Working Register Sets (reduces context switching) Clock Ma
dsPIC33EP64GS502 Datasheet
