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MT8VDDT1664HD - (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms

Datasheet Summary

Description

SYMBOL WE#, CAS#, RAS# TYPE DESCRIPTION Pin numbers may not correlate with symbols.

Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.

Features

  • 200-pin, small-outline, dual in-line memory module (SODIMM).
  • Fast data transfer rates PC1600, PC2100, or PC2700 www. DataSheet4U. com.
  • Utilizes 200 MT/s, 266 MT/s, and 333MT/s DDR SDRAM components.
  • 128MB (16 Meg x 64), 256MB (32 Meg x 64), or 512MB (64 Meg x 64).
  • VDD = VDDQ = +2.5V.
  • VDDSPD = +2.3V to +3.6V.
  • 2.5V I/O (SSTL_2 compatible).
  • Commands entered on each positive CK edge.
  • DQS edge-aligned with data for READs;.

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Datasheet preview – MT8VDDT1664HD

Datasheet Details

Part number MT8VDDT1664HD
Manufacturer MicrON Semiconductor Products
File Size 605.17 KB
Description (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms
Datasheet download datasheet MT8VDDT1664HD Datasheet
Additional preview pages of the MT8VDDT1664HD datasheet.

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Other Datasheets by Micron Semiconductor Products
  • MT8VDDT1664H - (MT8VDDT1664H / MT8VDDT3264H) 200-Pin DDR Sdram Sodimms
  • MT8VDDT1664A - (MT8VDDTxx64A) 184-Pin DDR Sdram Dimms
  • MT8VDDT3232U - (MT8VDDT3232U / MT8VDDT6432U) 100-Pin DDR Sdram Dimms
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  • MT8VDDT3264H - (MT8VDDT1664H / MT8VDDT3264H) 200-Pin DDR Sdram Sodimms
  • MT8VDDT3264HD - (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms
  • MT8VDDT6432U - (MT8VDDT3232U / MT8VDDT6432U) 100-Pin DDR Sdram Dimms
  • MT8VDDT6464A - (MT8VDDTxx64A) 184-Pin DDR Sdram Dimms

Full PDF Text Transcription

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128MB, 256MB, 512MB (x64) 200-PIN DDR SODIMM SMALL-OUTLINE DDR SDRAM MODULE Features • 200-pin, small-outline, dual in-line memory module (SODIMM) • Fast data transfer rates PC1600, PC2100, or PC2700 www.DataSheet4U.com • Utilizes 200 MT/s, 266 MT/s, and 333MT/s DDR SDRAM components • 128MB (16 Meg x 64), 256MB (32 Meg x 64), or 512MB (64 Meg x 64) • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O (SSTL_2 compatible) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Bidirectional data strobe (DQS) transmitted/received with data—i.e.
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