| Description | The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quadbank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.... |
| Features |
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data www.DataSheet4U.com capture (x16 has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on ... |
| Datasheet |
 46V16M8 Datasheet - 2.56MB |
