* VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
* Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data www.DataSheet4U.com captu.

The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quadbank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double d.

46V16M16

46V32M16

4600H

4600M

4600X

4604

4604T

4606

460DE08C3

4611

4612

4616

4622