46V16M8 Datasheet | Micron Technology

PRELIMINARY‡ 128Mb: x4, x8, x16 DDR SDRAM DOUBLE DATA RATE (DDR) SDRAM Features - VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V - Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data .. capture (x16 has two - one per byte) - Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle - Differential clock inputs (CK and CK#) - mands entered on each positive CK edge - DQS edge-aligned with data for READs; centeraligned with data for WRITEs - DLL to align DQ and DQS transitions with CK - Four internal banks for concurrent operation - Data mask (DM) for masking write data (x16 has two - one per byte) - x16 has programmable IOL/IOH option - Programmable burst lengths: 2, 4, or 8 - Auto precharge option - Auto Refresh and Self Refresh Modes - Longer lead TSOP for improved reliability (OCPL) - 2.5V I/O (SSTL_2 patible) MT46V32M4 - 8 Meg x 4 x 4 banks MT46V16M8 - 4 Meg x 8 x 4 banks MT46V8M16 - 2 Meg x 16 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: .micron./datasheets PIN ASSIGNMENT (TOP VIEW) 66-Pin TSOP x4 x8 x16 VDD VDD VDD NC DQ0 DQ0 VDDQ VDDQ VDDQ NC DQ1 NC DQ0 DQ1 DQ2 VSSQ VSSQ Vss Q NC DQ3 NC NC DQ2 DQ4 VDDQ VDDQ VDDQ NC DQ5 NC DQ1 DQ3 DQ6 VSSQ VSSQ Vss Q NC DQ7 NC NC NC NC VDDQ VDDQ VDDQ NC NC LDQS NC NC NC VDD VDD VDD NC DNU DNU NC NC LDM WE# WE# WE# CAS# CAS# CAS# RAS# RAS# RAS# CS# CS# CS# NC NC NC BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS DNU VREF VSS UDM CK# CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS x4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS OPTIONS - Configuration 32 Meg x 4 (8 Meg x 4 x 4 banks)...