46V16M8 - MT46V16M8

Micron Technology

Datasheet Details

The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits.

VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V.
Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data www. DataSheet4U. com capture (x16 has two.
one per byte).
Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle.
Differential clock inputs (CK and CK#).
Commands entered on each positive CK edge.
DQS edge-aligned with data for READs; centeraligned with data for WRIT.

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Published: Jun 30, 2008 |