MSP 34x5G
PRELIMINARY DATA SHEET
Contents
Page
Section
5 1.
6 1.1.
6 1.2.
7 1.3.
8 2.
9 2.1.
9 2.2.
9 2.2.1.
9 2.2.2.
10 2.2.3.
10 2.2.4.
10 2.2.5.
12 2.3.
12 2.4.
12 2.5.
12 2.5.1.
12 2.5.2.
12 2.5.3.
13 2.6.
13 2.6.1.
13 2.6.2.
13 2.7.
14 2.8.
14 2.9.
14 2.10.
15 3.
15 3.1.
15 3.1.1.
16 3.1.2.
16 3.1.3.
17 3.1.4.
17 3.1.4.1.
17 3.1.4.2.
17 3.1.4.3.
17 3.1.4.4.
17 3.2.
17 3.3.
17 3.3.1.
20 3.3.2.
21 3.3.2.1.
21 3.3.2.2.
21 3.3.2.3.
23 3.3.2.4.
25 3.3.2.5.
26 3.3.2.6.
Title
Introduction
Features of the MSP 34x5G Family and Differences to MSPD
MSP 34x5G Version List
MSP 34x5G Versions and their Application Fields
Functional Description
Architecture of the MSP 34x5G Family
Sound IF Processing
Analog Sound IF Input
Demodulator: Standards and Features
Preprocessing of Demodulator Signals
Automatic Sound Select
Manual Mode
Preprocessing for SCART and I2S Input Signals
Source Selection and Output Channel Matrix
Audio Baseband Processing
Automatic Volume Correction (AVC)
Loudspeaker Outputs
Quasi-Peak Detector
SCART Signal Routing
SCART DSP In and SCART Out Select
Stand-by Mode
I2S Bus Interface
ADR Bus Interface
Digital Control I/O Pins and Status Change Indication
Clock PLL Oscillator and Crystal Specifications
Control Interface
I2C Bus Interface
Internal Hardware Error Handling
Description of CONTROL Register
Protocol Description
Proposals for General MSP 34x5G I2C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start-Up Sequence: Power-Up and I2C-Controlling
MSP 34x5G Programming Interface
User Registers Overview
Description of User Registers
STANDARD SELECT Register
Refresh of STANDARD SELECT Register
STANDARD RESULT Register
Write Registers on I2C Subaddress 10hex
Read Registers on I2C Subaddress 11hex
Write Registers on I2C Subaddress 12hex
2
Micronas
