ZL30168 - Enhanced Quad Clock Translator

Product Overview

Microsemi

Datasheet Details

Part number	ZL30168
Manufacturer	Microsemi
File Size	725.32 KB
Description	Enhanced Quad Clock Translator
Datasheet	ZL30168 Datasheet
Additional preview pages of the ZL30168 datasheet.

Product details

Description

Precise Frequency Monitor (PFM) Guard Soak Timer (GST) Figure 14 "Typical Power-Up Reset and Configuration Circuit" 5.1, “ZL30168 Configuration programming“ Register Name: phasemem_limit_ref0 127 Register Name: dpll0_df_offset 187 13.0, “Package Markings“ Change Updated GPIO[5:6] power-up settings Clarified the PFM measurement interval Corrected the GST description Updated GPIO[5:6] power-up settings Added section 5.1 Corrected the 1ms phase memory limit example in the register description Co

Features

Four independent clock channels.
Programmable synthesizers generate any clockrate from 1 Hz to 750 MHz.
Four precision synthesizers generate clocks with maximum jitter below 0.63 ps RMS.
Four programmable digital PLLs/Numerically Controlled Oscillators (NCOs)/OTN clock generators based on buffer-fill levels.
Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz.
Flexible two-stage architecture translates between arbit.

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Published: Jan 21, 2024 |