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Mitel Networks Corporation

GP2010 Datasheet Preview

GP2010 Datasheet

GPS Receiver RF Front End

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GP2010
GPS Receiver RF Front End
Supersedes edition in August 1996 Global Positioning Products Handbook, HB4305-1.0
DS4056 - 3.4 October 1996
The GP2010 is Mitel Semiconductor second generation
RF Front-end for Global Positioning System (GPS) receivers.
The GP2010 uses many innovative design techniques and a
leading-edge bipolar process to offer a low power, low cost
and high reliability RF Front End solution . The GP2010 is
designed to operate from either 3 or 5 Volt power supplies.
The input to the device is the L1 (1575.42MHz) Coarse-
Acquisition (C/A) code Global Positioning signal from an
antenna (via a low-noise pre-amplifier). The output is 2-bit
quantised for subsequent signal processing in the digital
domain. The GP2010 contains an on-chip synthesiser, mixers,
AGC and a quantiser which provides Sign and Magnitude
digital outputs. A minimum of external components is required
to make a complete GPS front-end.
The device has been designed to operate with the GP2021
12-channel Global Positioning Correlator, and DW9255 SAW
filter, both also available from Mitel Semiconductor.
FEATURES
s Low Voltage Operation (3V - 5V)
s Low Power - 200mW typ. (3V supply)
s C/A Code Compatible
s On-chip PLL Including Complete VCO
s Triple Conversion Receiver
s 44-Lead Surface Mount Quad Flat-Pack Package
s Sign and Magnitude Digital Outputs
s Compatible with GP2021 CMOS Correlator
APPLICATIONS
s C/A Code Global Positioning by Satellite Receivers
s Time Standards
s Navigation
s Surveying
ORDERING INFORMATION
The GP2010 is available in 44 pin Quad Flat pack (gullwing
formed leads) to Industrial (-40°C to +85°C) grade.
ORDERING CODE
GP2010 IG GPBR Industrial - Plastic 44-pin PQFP
34 22
35 21
36 20
37 19
38
39
GP2010
18
17
40 16
41 15
42 14
43 13
44 12
GP44
Pin Name
1 IF Output
2 PLL Filter 1
3 PLL Filter 2
4 VEE (OSC)
5 VCC (OSC)
6 VEE (OSC)
7 VEE (REG)
8 PRef
9 PReset
10 VEE (IO)
11 CLK
12 MAG
13 SIGN
14 OPCIK-
15 OPCIK+
16 VDD (IO)
17 PDN
18 TEST
19 LD
20 VEE (DIG)
21 AGC -
22 AGC +
Pin Name
23 VCC (DIG)
24 REF 2
25 REF 1
26 VCC (RF)
27 VEE (RF)
28 VEE (RF)
29 RF Input
30 VEE (RF)
31 VEE (RF)
32 VCC (RF)
33 O/P 1-
34 O/P 1+
35 VCC (2)
36 I/P 2-
37 I/P 2+
38 VEE (IF)
39 VEE (IF)
40 O/P 2-
41 O/P 2+
42 VCC (3)
43 I/P 3-
44 I/P 3+
Fig. 1 Pin connections - top view
RELATED PRODUCTS AND PUBLICATIONS
Part
Description
Data
Reference
DW9255
GP2021
GPSBuilder-2
GP2010
GP2015
GP2015
35.42MHz SAW Filter
Twelve-Channel Correlator
Twelve-Channel GPS receiver
development system
Design with the GP2010
Small RF Format Front End
Design with the GP2015
DS3861
DS4057
DS4004
AN4364
DS4374
AN4533




Mitel Networks Corporation

GP2010 Datasheet Preview

GP2010 Datasheet

GPS Receiver RF Front End

No Preview Available !

GP2010
ABSOLUTE MAXIMUM RATINGS
(Non-simultaneous)
Max. Supply Voltage
7V
Max. RF Input
+15dBm
Max. voltage on any pin
VCC/VDD + 0.5V
except LD (pin 19) and PReset (pin 9), which are 5.5V
Min. voltage on any pin
Storage Temperature
VEE - 0.5V
-65°C to +150°C
Operation Junction Temperature
-40°C to +150°C
10MHz Reference Input
1.5V pk -pk
ESD PROTECTION
The GP2010 device is static sensitive. The most
sensitive pins withstand a 750V test by the human body
model. Therefore, ESD handling precautions are essential to
avoid degradation of performance or permanent damage to
this device.
PRODUCT DESCRIPTION
The GP2010 receives the 1575.42MHz signal
transmitted by GPS satellites and converts it to a 4.309MHz
IF, using a triple down-conversion. The 4.309MHz IF is
sampled to produce a 2-bit digital output. If the GP2010 is
used in conjunction with the GP2021 correlator, then the
GP2021 provides a sampling clock of 5.714MHz. This converts
the IF to a 1.405MHz 2-bit digital output at TTL levels.
The GP2010 can operate from a single supply from
+3V (nominal) to +5V (nominal).
A block diagram of the circuit is shown in figure 2.
IF STRIP
The input signal to the GP2010 is the GPS L1 signal
received via an antenna and a suitable LNA. The L1 input is
a spread spectrum signal at 1575.42MHz with 1.023Mbps
BPSK modulation. The signal level at the antenna is about
-130dBm, spread over a 2.046MHz bandwidth, so the wanted
signal is actually buried in noise. The high RF input compression
point of the GP2010 means that with subsequent IF filtering
it is possible to reject large out of band jamming signals, in
particular 900MHz as used by mobile telephones.The on-chip
PLL generates the first local-oscillator frequency at 1400MHz.
The output of the front-end mixer (Stage 1) at 175.42 MHz can
then be filtered before being applied to the second stage. The
double-balanced stage 1 mixer outputs are open-collectors,
and require external dc bias to VCC.
The second stage contains further gain and a mixer
with a local oscillator signal at 140 MHz giving a second IF at
35.42 MHz. The second stage mixer is also double-balanced
with open-collector outputs requiring external dc bias to VCC.
The signal from stage 2 is passed through an external
filter with a 1dB bandwidth of 1.9MHz. The performance of this
filter is critical to system performance and it is recommended
that a SAW filter is used (part number DW9255, also available
from Mitel Semiconductor). The output of the filter then feeds
the main IF amplifier. This includes 2 AGC amplifiers and a
third mixer with a local oscillator signal at 31.111 MHz giving
a final IF at 4.309 MHz. There is an on-chip filter after the third
mixer which provides filtering centred on 4.309 MHz. The IF
output, which has 1koutput impedance, is provided for test
purposes. All of the signals within the IF amplifier are differential
including the filter inputs and outputs, except the IF output (pin
1), to reduce any common mode interference.
175.42MHz FILTER
(33,34)
(36,37)
35.42MHz FILTER
(40,41)
(43,44)
AGC CAPACITOR
(21) (22)
(29)
RF Input
L1
(1575.42MHz)
FRONT
END
MIXER
1. 400GHz
2nd
STAGE
MIXER
140MHz
AGC
AGC
3rd
STAGE
MIXER
4.3MHz
FILTER
31.11MHz
(1)
IF Output
(4.309MHz)
VCO
EXTERNAL
LOOP
FILTER
(2)
(3)
VOLTAGE
REGULATOR
PLL
LOOP
FILTER
PLL LOCK
LOGIC O/P
(LD)
(19)
PLL REF I/P
10MHz (REF 2)
(24)
PHASE
DETECTOR
PLL
REFERENCE
OSCILLATOR
÷5 ÷52
÷7 ÷9
÷4
1.400GHz
PHASE-
LOCKED
LOOP
AGC
CONTROL
+1.21V
_
+
POWER-ON
RESET
POWER
CONTROL
REF 1 I/P
(FOR USE WITH
CRYSTAL REF
ONLY)
(25)
(14, 15)
40MHz CLOCK O/P
(FOR CORRELATOR
CHIP)
(OPCIK +/-)
(18) (8)
BITE
(TEST)
POWER-ON
REFERENCE
I/P
(PREF)
(17)
POWER
DOWN I/P
(PDn)
(9)
POWER-ON
RESET O/P
(PRESET)
Fig. 2 Block diagram of GP2010
+Vr
-Vr
SIGN
O/P
LATCH
MAG
O/P
LATCH
A -> D
CONVERTER
(13)
SIGN
TTL O/P
(12)
MAG
TTL O/P
(11) SAMPLE
CLOCK I/P (CLK)
(5.71MHz TTL)
2


Part Number GP2010
Description GPS Receiver RF Front End
Maker Mitel Networks Corporation
Total Page 24 Pages
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