900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Mitel Networks Corporation

PDSP16488GC Datasheet Preview

PDSP16488GC Datasheet

Single Chip 2D Convolver with Integral Line Delays

No Preview Available !

PDSP16488A
Single Chip 2D Convolver with Integral Line Delays
Advance Information
Supersedes version in 1996 Media IC Handbook, HB4599-1.0
and the PDSP16488A MA data sheet, DS3742
DS3713 - 6.4 December 1997
The PDSP16488A is a fully integrated, application specific,
image processing device. It performs a two dimensional convo-
lution between the pixels within a video window and a set of
stored coefficients. An internal multiplier accumulator array can
be multi-cycled at double or quadruple the pixel clock rate. This
then gives the window size options listed in Table 1.
An internal 32kbit RAM can be configured to provide either
four or eight line delays. The length of each delay can be
programmed to the users requirement, up to a maximum of 1024
pixels per line. The line delays are arranged in two groups,which
may be internally connected in series or may be configured to
accept separate pixel inputs. This allows interlaced video or
frame to frame operations to be supported.
The 8-bit coefficients are also stored internally and can be
downloaded from a host computer or from an EPROM. No
additional logic is required to support the EPROM and a single
device can support up to 16 convolvers.
The PDSP16488A contains an expansion adder and delay
network which allows several devices to be cascaded. Con-
volvers with larger windows can then be fabricated as shown in
Table 2.
Intermediate 32-bit precision is provided to avoid any danger
of overflow, but the final result will not normally occupy all bits.
The PDSP16488A thus provides a gain control block in the
output path, which allows the user to align the result to the most
significant end of the 32-bit word.
Pixel Window size Maximum pixel
size Width Depth rate (MHz)
Line delays
84
88
88
16 4
16 8
4
4
8
4
4
20
20
10
20
10
431024
431024
83512
43512
43512
Table 1 Single PDSP16488A configurations
COMPOSITE
DATA
PIXEL
CLOCK
GEN
SYNC
SYNC
EXTRACT
ODD FIELD
ADC
OPTIONAL
FIELD
DELAY
EPROM POWER
ON
ADDR DATA RESET
CLK
HRES
BYPASS
RES
DELOP
DELAYED
SYNC
PDSP16488A
L7:0 D15:0
OUTPUT
DATA
IP7:0
Fig. 1 Typical stand-alone real time system
FEATURES
s The PDSP16488A is a replacement for the
PDSP16488 (see Note below)
s 8 or 16-bit Pixels with rates up to 40 MHz
s Window Sizes up to 838 with a Single Device
s Eight Internal Line Delays
s Supports Interlace and Frame-to-Frame Operations
s Coefficients Supplied from an EPROM or Remote Host
s Expandable in both X and Y for Larger Windows
s Gain Control and Pixel Output Manipulation
s 84-pin PGA or 132-pin QFP Package Options
Note: PDSP16488A devices are not guaranteed to cascade with
PDSP16488 devices. Mitel Semiconductor do not recommend
that PDSP16488A be mixed with PDSP16488 devices in a single
equipment design. The PDSP16488A requires external pullup
resistors in EPROM Mode (see Static Electrical Characteristics).
Max.
pixel Pixel
No. of PDSP16488As for N3N window size
rate size
(MHz)
333 535 737 939 11311 15315 23323
10 8 1 1 1 4 4
10 16 1 2 2 - -
20 8 1 2 2 6 6
20 16 1 4 4 - -
40 8 1 4* 4* - -
40 16 2 - - - -
4
-
8
-
-
-
9
-
-
-
-
-
*Maximum rate is limited to 30MHz by line store expansion delays
Table 2 PDSP16488As needed to implement typical window sizes
ORDERING INFORMATION
Commercial (0°C to 170°C)
PDSP16488A / C0 / AC (PGA)
Industrial (240°C to 185°C)
PDSP16488A / B0 / AC (PGA)
PDSP16488A / B0 / GC (QFP)
Military (255°C to 1125°C)
PDSP16488A / A0 / AC (PGA)
PDSP16488A / A0 / GC (QFP)
PDSP16488A / MA / ACBR (PGA) MIL-STD-883 Class B*
PDSP16488A / MA / GCPR (QFP) MIL-STD-883 Class B*
*See Notes following Static Electrical CharacteristicsTable




Mitel Networks Corporation

PDSP16488GC Datasheet Preview

PDSP16488GC Datasheet

Single Chip 2D Convolver with Integral Line Delays

No Preview Available !

Signal
IP7:0
L7:0
BYPASS
HRES
X15:0
D15:0
PC1
PC0
DELOP
DS
CE
Type
Input
I/O
Input
Input
Dual
function
Output
Output
Input
Output
I/O
Input
R/W
PROG
Input
I/O
CLK Input
BIN
OVR
RES
SINGLE
MASTER
OEN
CS3:0
F1:0
VDD
GND
Output
Output
Input
Input
Input
Input
Outputs
Outputs
Power
Power
2
Description
Pixel data input to the first line delay (most significant byte in 16-bit mode).
Pixel data input to the second group of line delays. (least significant byte in 16-bit mode). Alterna-
tively an output from the last line delay when the appropriate mode bit is set.
The first line delay in the first group is bypassed when this input is high. No internal pullup resistor.
Resets the line delay address pointers when high. Normally the composite sync signal in real time
applications. In non real time systems it defines a frame store update period, when low.
Address/data connections from a Master or Single device to the external coefficient source,
with X15 defining EPROM or Host support. Otherwise they provide the expansion data input.
Signed 16-bit scaled data or multiplexed 32-bit intermediate data. During intermediate transfers the
most significant half is valid when the clock is low, and the least significant half when clock is high.
During programming a Master device outputs a timing strobe on this pin. This is passed down
the chain in a multiple device system, using the PC0 input on the next device.
This pin is used in conjunction with PC1 in multiple device systems. It terminates the write strobe
from a Master device which is EPROM supported.
This output provides a version of the HRES input which has been delayed by an amount defined by
the user.
The data strobe from a host computer, active low. This pin will be an output from an EPROM
supported Master device which provides strobes to the remaining devices.
An active low enable which is internally gated with R/W and DS to perform reads or writes to the
internal registers. In a Single or Master device, which is supported from an EPROM, the
bottom 72 addresses are always used and CE is not needed. CE can then be used to initiate a
new register load sequence after the power on load sequence.
Read / not write line from the host CPU. When an EPROM is used this pin should be tied low.
This pin is normally an input which signifies that registers are to be changed or examined. It is,
however, an output from an EPROM supported Single or Master device indicating to the rest
of the system that registers are being updated.
Clock. All events are triggered on the rising edge of CLK, except the latching of least significant
expansion inputs . Internally the clock can be multiplied by two or four in order to increase the
effective number of multipliers.
This output indicates the result from the internal comparison. A high value indicates that the pixel
was greater than the internal threshold. The output is only valid from the last device in a chain.
When high this output indicates that there has been a gain control overflow.
Active low power on reset signal.
Tied to ground to indicate a Single device system. Internal pullup resistor.
Tied to ground to indicate the Master device in a multiple device system. Must be left open circuit
in a Single device system. Internal pullup resistor.
Output enable signal. Active low.
Four address bits from a Master specifying one of sixteen devices in a multiple device system.
Must be externally decoded to provide chip enables for the additional devices.
These bits indicate the field selection given by the gain control auto select logic. The same coding
as that used for Control Register bits C5:4 is used.
15V supply. All VDD pins must be connected.
0V supply. All GND pins must be connected.
Table 3 Signal descriptions


Part Number PDSP16488GC
Description Single Chip 2D Convolver with Integral Line Delays
Maker Mitel Networks Corporation
Total Page 30 Pages
PDF Download

PDSP16488GC Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 PDSP16488GC Single Chip 2D Convolver with Integral Line Delays
Mitel Networks Corporation
2 PDSP16488GCPR (QFP) MIL-S Single Chip 2D Convolver with Integral Line Delays
Mitel Networks Corporation





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy