M5M4V16G50DFP-12 Datasheet | Mitsubishi Electric

DESCRIPTION The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V16G50DFP can operate at frequencies of 100+ MHz. The BLOCK WRITE and WRITE-PER-BIT functions provide improved performance in graphic memory systems. FEATURES - Single 3.3v±0.3v power supply - Clock frequencies of 125 MHz - Fully synchronous operation referenced to clock rising edge - Dual bank operation controlled by A10(Bank Address) - Internal pipelined operation: column address can be changed every clock cycle - Programmable /CAS Latency (LVTTL: 2 and 3) - Programmable Burst Length (1/2/4/8 and Full Page) - Programmable Burst Type (Sequential / Interleave) - Byte control using DQM0 - DQM3 signals in both read and write cycles - Persistent Write-Per-Bit (WPB) function - 8 Column Block Write (BW) function - Auto Precharge / All bank precharge controlled by A9 - Auto Refresh and Self Refresh Capability - 2048 refresh cycles /32ms - LVTTL Interface - 100 pin QFP package with 0.65mm lead pitch Max. Frequency M5M4V16G50DFP - 8 M5M4V16G50DFP- 10 M5M4V16G50DFP- 12 125MHz 100MHz 83MHz CLK Access Time 7ns 8ns 10ns MITSUBISHI ELECTRIC SGRAM (Rev. 0.0) Jan'97 Preliminary MITSUBISHI LSIs M5M4V16G50DFP -8, -10, -12 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM CLK CKE /CS /RAS /CAS /WE DSF A0-10 A0-9 A0-7 A10 DQ0-31 DQM0-3 Vdd Vdd Q Vss Vss Q : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Special Function Enable : Address Input : Row Address inputs : Column Address inputs : Bank Address : Data I/O : Output Disable/ Write Mask : Power Supply : Power Supply for Output : Ground : Ground for Output MITSUBISHI ELECTRIC 14 VDD 15 VSS 16 DQ20 17 DQ21 18 VSSQ 19 DQ22 20 DQ23 21 VDDQ 22 DQM0 23 DQM2 24 /WE 25 /CAS 26 /RAS 27 /CS 28 A10 29 A8 30 10 11 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ 12...