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Mitsubishi

M5M4V64S20ATP-8L Datasheet Preview

M5M4V64S20ATP-8L Datasheet

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

No Preview Available !

SDRAM (Rev.1.3)
Mar98
MITSUBISHI LSIs
M5M4V64S20ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
M5M4V64S20ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
in computer systems.
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz /100MHz
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A9
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
M5M4V64S30ATP-8A
M5M4V64S30ATP-8
M5M4V64S30ATP-10
Max.
Frequency
125MHz
100MHz
100MHz
CLK Access
Time
6ns
6ns
8ns
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
Vdd
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-3
DQM
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
PIN CONFIGURATION
(TOP VIEW)
1 54 Vss
2 53 NC
3 52 VssQ
4 51 NC
5 50 DQ3
6 49 VddQ
7 48 NC
8 47 NC
9 46 VssQ
10 45 NC
11 44 DQ2
12 43 VddQ
13 42 NC
14 41 Vss
15 40 NC
16 39 DQM
17 38 CLK
18 37 CKE
19 36 NC
20 35 A11
21 34 A9
22 33 A8
23 32 A7
24 31 A6
25 30 A5
26 29 A4
27 28 Vss
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
1




Mitsubishi

M5M4V64S20ATP-8L Datasheet Preview

M5M4V64S20ATP-8L Datasheet

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

No Preview Available !

SDRAM (Rev.1.3)
Mar98
MITSUBISHI LSIs
M5M4V64S20ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
BLOCK DIAGRAM DQ0-3
I/O Buffer
Memory Array Memory Array Memory Array Memory Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
A0-11 BA0,1
Clock Buffer
/CS /RAS /CAS /WE DQM
CLK CKE
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 5M 4 V 64 S 2 0 A TP - 8
Access Item
Package Type TP: TSOP(II)
Process Generation
Function 0: Random Column, 1: 2N-rule
Organization 2n 2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 64:64M bits
Interface S: SSTL, V:LVTTL
Memory Style (DRAM)
Use, Recommended Operating Conditions, etc
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
2


Part Number M5M4V64S20ATP-8L
Description 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
Maker Mitsubishi
Total Page 30 Pages
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