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145106P - MC145106P

Description

P0 P8 Programmable Inputs (PDIP Pins 17 9; SOG Pins 19, 17 14, 12

9) Programmable divider inputs (binary).

Pin 2) Frequency input to programmable divider (derived from VCO).

Features

  • fset value is determined by the 11.31 MHz crystal frequency and is 10.7 MHz for the example. The VHF marine synthesizer in Figure 4 depicts a single loop approach for FM transceivers. The VCO operates on frequency during transmit and is offset downward during receive. The offset corresponds to the receive IF (10.7 MHz) for channels having identical receive/transmit frequencies (simplex), and is (10.7.
  • 4.6 = 6.1) MHz for duplex channels. Carrier modulation is introduced in the loop durin.

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Full PDF Text Transcription

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC145106/D MC145106 PLL Frequency Synthesizer CMOS The MC145106 is a phase–locked loop (PLL) frequency synthesizer constructed in CMOS on a single monolithic structure. This synthesizer finds applications in such areas as CB and FM transceivers. The device contains an oscillator/amplifier, a 210 or 211 divider chain for the oscillator signal, a programmable divider chain for the input signal, and a phase detector. The MC145106 has circuitry for a 10.24 MHz oscillator or may operate with an external signal. The circuit provides a 5.12 MHz output signal, which can be used for frequency tripling. A 29 programmable divider divides the input signal frequency for channel selection.
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