54LS161A Datasheet | Motorola Semiconductor

BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous counters. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS160A and LS162A count modulo 10 (BCD). The LS161A and LS163A count modulo 16 (binary.) The LS160A and LS161A have an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge. BCD (Modulo 10) Binary (Modulo 16) Asynchronous Reset LS160A LS161A Synchronous Reset LS162A LS163A - Synchronous Counting and Loading - Two Count Enable Inputs for High Speed Synchronous Expansion - Terminal Count Fully Decoded - Edge-Triggered Operation - Typical Count Rate of 35 MHz - ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC TC Q0 Q1 Q2 Q3 CET PE 16 15 14 13 12 11 10 9 - R CP P0 P1 P2 P3 CEP GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. - MR for LS160A and LS161A - SR for LS162A and LS163A PIN NAMES P0 - P3 CEP Q0 - Q3 TC Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs (Note b) Terminal Count Output (Note...