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Motorola Electronic Components Datasheet

56F805 Datasheet

16-bit Hybrid Controller

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Freescale Semiconductor, Inc.
DSP56F805/D
Rev. 12.0, 02/2004
56F805
Technical Data
56F805 16-bit Hybrid Controller
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• 31.5K × 16-bit words Program Flash
• 512 × 16-bit words Program RAM
• 4K × 16-bit words Data Flash
• 2K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Up to 64K × 16-bit words each of external
Program and Data memory
• Two 6-channel PWM Modules
• Two 4-channel, 12-bit ADCs
• Two Quadrature Decoders
• CAN 2.0 B Module
• Two Serial Communication Interfaces (SCIs)
• Serial Peripheral Interface (SPI)
• Up to four General Purpose Quad Timers
• JTAG/OnCETM port for debugging
• 14 Dedicated and 18 Shared GPIO lines
• 144-pin LQFP Package
6
PWM Outputs
Current Sense Inputs
3
Fault Inputs
4
6
PWM Outputs
Current Sense Inputs
3
Fault Inputs
4
A/D1
4 A/D2 ADC
4 VREF
Quadrature
Decoder 0/
4 Quad Timer A
PWMA
PWMB
RSTO
EXTBOOT
RESET IRQB
IRQA
6
JTAG/
OnCE
Port
VPP VCAPC VDD
28
VSS
8*
VDDA
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quadrature
Decoder 1/
Program Memory
4
Quad B Timer
32252 x 16 Flash
512 x 16 SRAM
Quad Timer C
••
PAB
PDB
16-Bit
PLL
CLKO
2 Boot Flash
Quad Timer D
2048 x 16 Flash
4 / Alt Func
CAN 2.0A/B
Data Memory
2
SCI0
4096 x 16 Flash
2048 x 16 SRAM
or
2 GPIO
56800
XDB2
Core
CGDB
• • •XAB1
XAB2
INTERRUPT
IPBB
Clock Gen
XTAL
EXTAL
SCI1
or
COP/
CONTROLS CONTROLS
16 16
External 6
Address Bus
A[00:05]
A[06:15] or
2 GPIO
Watchdog
COP RESET
SPI
Application-
MODULE CONTROLS
or Specific
4
GPIO
Memory &
Dedicated
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
External
Bus
Interface
Unit
Switch
External
Data Bus
Switch
Bus
GPIO-E2:E3 &
10 GPIO-A0:A7
D[00:15]
16
PS Select
DS Select
GPIO
Peripherals
Control
WR Enable
14 RD Enable
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F805 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com


Motorola Electronic Components Datasheet

56F805 Datasheet

16-bit Hybrid Controller

No Preview Available !

www.DataSheet4U.com
Freescale Semiconductor, Inc.
Part 1 Overview
1.1 56F805 Features
1.1.1 Digital Signal Processing Core
• Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface
1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
— 31.5K × 16 bit words of Program Flash
— 512 × 16-bit words of Program RAM
— 4K× 16-bit words of Data Flash
— 2K × 16-bit words of Data RAM
— 2K × 16-bit words of Boot Flash
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K × 16 bits of Data memory
— As much as 64K × 16 bits of Program memory
1.1.3 Peripheral Circuits for 56F805
• Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
four Fault inputs, fault tolerant design with dead time insertion; supports both center- and edge-
aligned modes
• Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions;
ADC and PWM modules can be synchronized
• Two Quadrature Decoders each with four inputs or two additional Quad Timers
2 56F805 Technical Data
For More Information On This Product,
Go to: www.freescale.com


Part Number 56F805
Description 16-bit Hybrid Controller
Maker Motorola
Total Page 30 Pages
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