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Motorola Electronic Components Datasheet

MC100E196 Datasheet

PROGRAMMABLE DELAY CHIP

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Programmable Delay Chip
The MC10E/100E196 is a programmable delay chip (PDC) designed
primarily for very accurate differential ECL input edge placement
applications.
The delay section consists of a chain of gates and a linear ramp delay
adjust organized as shown in the logic symbol. The first two delay
elements feature gates that have been modified to have delays 1.25 and
1.5 times the basic gate delay of approximately 80 ps. These two
elements provide the E196 with a digitally-selectable resolution of
approximately 20 ps. The required device delay is selected by the seven
address inputs D[0:6], which are latched on chip by a high signal on the
latch enable (LEN) control.
The FTUNE input takes an analog voltage and applies it to an internal
linear ramp for reducing the 20 ps resolution still further. The FTUNE input
is what differentiates the E196 from the E195.
An eighth latched input, D7, is provided for cascading multiple PDC’s
for increased programmable range. The cascade logic allows full control
of multiple PDC’s, at the expense of only a single added line to the data
bus for each additional PDC, without the need for any external gating.
MC10E196
MC100E196
PROGRAMMABLE
DELAY CHIP
2.0ns Worst Case Delay Range
20ps/Delay Step Resolution
Linear Input for Tighter Resolution
>1.0GHz Bandwidth
On Chip Cascade Circuitry
Extended 100E VEE Range of –4.2 to –5.46V
75KInput Pulldown Resistors
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
PIN NAMES
Pin
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
Function
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Min Delay Set
Max Delay Set
Cascade Signal
Linear Voltage Input
VBB
IN
IN
11
EN * 1.25
0
1
* 1.5
0
1
LEN
SET MIN
SET MAX
0
11
LOGIC DIAGRAM – SIMPLIFIED
0
1 11
4 GATES
0
1
7 BIT LATCH
8 GATES
0
1
16 GATES
LEN Q
LATCH
D
FTUNE
0
1
0
11
CASCADE
LINEAR
RAMP
Q
Q
CASCADE
CASCADE
D0 D1 D2 D3 D4 D5 D6
* DELAYS ARE 25% OR 50% LONGER THAN
* STANDARD (STANDARD 80 PS)
D7
12/93
© Motorola, Inc. 1996
2–1
REV 2


Motorola Electronic Components Datasheet

MC100E196 Datasheet

PROGRAMMABLE DELAY CHIP

No Preview Available !

MC10E196 MC100E196
Pinout: 28-Lead PLCC (Top View)
D2 D3 D4 D5 D6 D7 NC
25 24 23 22 21 20 19
D1 26
18 FTUNE
D0 27
17 NC
LEN 28
VEE 1
16 VCC
15 VCCO
IN 2
IN 3
14 Q
13 Q
VBB 4
56 7
NC NC EN
8
12 VCCO
9 10 11
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit Condition
IIH Input HIGH Current
IEE Power Supply Current
10E
100E
150
130 156
130 156
150
130 156
130 156
150
130 156
150 179
µA
mA
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
Symbol
tPLH
tPHL
tRANGE
t
Lin
tSKEW
Characteristic
Propagation Delay
IN to Q; Tap = 0
IN to Q; Tap = 127
EN to Q; Tap = 0
D7 to CASCADE
Programmable Range
tPD (max) – tPD (min)
Step Delay
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
Linearity
Duty Cycle Skew
tPHL–tPLH
0°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max
1210
3320
1250
300
1360
3570
1450
450
1510
3820
1650
700
1240
3380
1275
300
1390
3630
1475
450
1540
3880
1675
700
1440
3920
1350
300
1590
4270
1650
450
1765
4720
1950
700
2000 2175
2050 2240
2375 2580
55
115
250
505
1000
D1
17
34
68
136
272
544
1088
D0
105
180
325
620
1190
55
115
250
515
1030
D1
17.5
35
70
140
280
560
1120
D0
105
180
325
620
1220
65
140
305
620
1240
D1
21
42
84
168
336
672
1344
D0
120
205
380
740
1450
±30 ±30 ±30
Unit
ps
ps
ps
ps
Notes
6
7
1
MOTOROLA
2–2 ECLinPS and ECLinPS Lite
DL140 — Rev 4


Part Number MC100E196
Description PROGRAMMABLE DELAY CHIP
Maker Motorola
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MC100E196 Datasheet PDF






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