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MC100E211 Datasheet

1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:6 Differential Clock
Distribution Chip
The MC10E/100E211 is a low skew 1:6 fanout device designed
explicitly for low skew clock distribution applications. The device can be
driven by either a differential or single-ended ECL or, if positive power
supplies are used, PECL input signal (PECL is an acronym for Positive
ECL, PECL levels are ECL levels referenced to +5V rather than ground).
If a single-ended input is to be used the VBB pin should be connected to
the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB
supply is designed to act as the switching reference for the input of the
E211 under single-ended input conditions, as a result this pin can only
source/sink up to 0.5mA of current.
MC10E211
MC100E211
1:6 DIFFERENTIAL
CLOCK DISTRIBUTION CHIP
Guaranteed Low Skew Specification
Synchronous Enabling/Disabling
Multiplexed Clock Inputs
VBB Output for Single-Ended Use
Internal 75kInput Pulldown Resistors
Common and Individual Enable/Disable Control
High Bandwidth Output Transistors
Extended 100E VEE Range of –4.2V to –5.46V
The E211 features a multiplexed clock input to allow for the distribution
of a lower speed scan or test clock along with the high speed system
clock. When LOW (or left open in which case it will be pulled LOW by the
input pulldown resistor) the SEL pin will select the differential clock input.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next
negative transition of the CLK (or SCLK) input. The enabling function is synchronous so that the outputs will only be
enabled/disabled when the outputs are already in the LOW state. In this way the problem of runt pulse generation during the
disable operation is avoided. Note that the internal flip flop is clocked on the falling edge of the input clock edge, therefore all
associated specifications are referenced to the negative edge of the CLK input.
The output transitions of the E211 are faster than the standard ECLinPSedge rates. This feature provides a means of
distributing higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits
guaranteed in the specification, there are certain termination guidelines which must be followed. For more details on the
recommended termination schemes please refer to the applications information section of this data sheet.
FUNCTION TABLE
CLK
SCLK
SEL
H/L X
X H/L
Z* Z*
L
H
X
* Z = Negative transition of CLK or SCLK
ENx
L
L
H
Q
CLK
SCLK
L
ECLinPS is a trademark of Motorola Inc.
5/95
© Motorola, Inc. 1996
2–1
REV 3


Motorola Electronic Components Datasheet

MC100E211 Datasheet

1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP

No Preview Available !

MC10E211 MC100E211
EN4 EN5 VCC0 Q5 Q5 Q4 Q4
25 24 23 22 21 20 19
EN3 26
18 Q3
SEL 27
17 Q3
SCLK 28
VEE 1
16 VCC
15 Q2
CLK 2
14 Q2
CLK 3
13 Q1
VBB 4
5
6
12 Q1
7 8 9 10 11
CEN EN2 EN1 EN0 VCC0 Q0 Q0
Pinout: 28-Lead PLCC (Top View)
EN0
CLK
CLK
SCLK
SEL
EN1-4
CEN
0
1
DQ
BITS 1-4
DQ
EN5 DQ
VBB
Logic Diagram
Q0
Q0
Q1-4
Q1-4
Q5
Q5
MOTOROLA
2–2 ECLinPS and ECLinPS Lite
DL140 — Rev 4


Part Number MC100E211
Description 1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
Maker Motorola
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MC100E211 Datasheet PDF






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