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Motorola Electronic Components Datasheet

MC100LVEL33 Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
÷4 Divider
The MC100LVEL33 is an integrated ÷4 divider. The differential clock
inputs and the VBB allow a differential, single-ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a 0.01µF capacitor. Also note that the VBB is designed to be
used as an input bias on the EL33 only, the VBB output has limited current
sink and source capability. The LVEL is functionally equivalent to the
EL33 and works from a low voltage supply.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flops will attain a random state; the reset
allows for the synchronization of multiple LVEL33’s in a system.
630ps Propagation Delay
4.0GHz Toggle Frequency
High Bandwidth Output Transitions
Operates from –3.3V (or 3.3V) Supply
75kInternal Input Pulldown Resistors
>2000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Reset 1
CLK 2
CLK 3
8 VCC
R
7Q
÷4
6Q
VBB 4
5 VEE
MC100LVEL33
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
PIN DESCRIPTION
PIN
CLK
Reset
VBB
Q
FUNCTION
Clock Inputs
Asynch Reset
Ref Voltage Output
Data Ouputs
8/96
© Motorola, Inc. 1996
3–1
REV 0


Motorola Electronic Components Datasheet

MC100LVEL33 Datasheet

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MC100LVEL33
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C
0°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
IEE
VEE
VBB
IIH
IIL
Power Supply Current
33 37
33 37
33 37
35 39 mA
Power Supply Voltage
–3.0
–3.8 –3.0
–3.8 –3.0
–3.8 –3.0
–3.8 V
Output Reference Voltage –1.38
–1.26 –1.38
–1.26 –1.38
–1.26 –1.38
–1.26 V
Input HIGH Current
150 150 150 150 µA
Input LOW Current CLK –600
Other 0.5
–600
0.5
–600
0.5
–600
0.5
µA
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C
0°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
fMAX
Maximum Toggle
Frequency
3.4 4.2
3.8 4.2
3.8 4.2
3.8 4.2
GHz
tPLH
tPHL
Propagation Delay
CLK to Q (Diff)
CLK to Q (SE)
Reset to Q
510
460
500
690 530
740 480
700 510
710 540
760 490
710 520
720 600
770 550
720 580
780
830
780 ps
trr
tskew
VPP
VCMR
Reset Recovery
Duty Cycle Skew2
Minimum Input Swing1
Common Mode Range3
VPP < 500mV
VPP 500mV
300
150
–2.0
–1.8
300
20
150
–0.4 –2.1
–0.4 –1.9
300
20
150
–0.4 –2.1
–0.4 –1.9
300
20
150
–0.4 –2.1
–0.4 –1.9
ps
20 ps
mV
V
–0.4
–0.4
tr Output Rise/Fall Times Q 120
tf (20% – 80%)
320 120
320 120
320 120
320 ps
1. Minimum input swing for which AC parameters are guaranteed.
2. Duty cycle skew is the difference between TPLH and TPLL.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V – |VCMR(min)|.
CLK
RESET
Q
Figure 1. Timing Diagram
MOTOROLA
3–2 ECLinPS and ECLinPS Lite
DL140 — Rev 3


Part Number MC100LVEL33
Description Divider
Maker Motorola
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MC100LVEL33 Datasheet PDF






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