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MC10E160 - 12-Bit Parity Generator/Checker

Download the MC10E160 datasheet PDF. This datasheet also covers the MC100E160 variant, as both devices belong to the same 12-bit parity generator/checker family and are provided as variant models within a single manufacturer datasheet.

Features

  • an output register. Multiplexers direct the register input, giving the option of holding present data by asserting HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT HIGH. The output register itself is clocked by a positive edge on CLK1 or CLK2 (or both). A HIGH on the reset pin (R) overrides to force the Y output LOW. 12-BIT PARITY.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MC100E160_Motorola.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MC10E160 12-BIT PARITY GENERATOR/CHECKER ON Semiconductor
MC10E163 2-BIT 8:1 MULTIPLEXER ON Semiconductor
MC10E164 16:1 MULTIPLEXER ON Semiconductor
MC10E1651 Dual ECL Output Comparator ON Semiconductor
MC10E1652 Dual ECL Output Comparator ON Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MC10E163 2-Bit 8:1 Multiplexer
MC10E164 16:1 MULTIPLEXER
MC10E1651 DUAL ECL OUTPUT COMPARATOR
MC10E1652 DUAL ECL OUTPUT COMPARATOR
MC10E166 9-BIT MAGNITUDE COMPARATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA 12ĆBit Parity Generator/Checker MC10E160 MC100E160 The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The E160 also features an output register. Multiplexers direct the register input, giving the option of holding present data by asserting HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT HIGH. The output register itself is clocked by a positive edge on CLK1 or CLK2 (or both). A HIGH on the reset pin (R) overrides to force the Y output LOW. 12-BIT PARITY GENERATOR/CHECKER • • • • • • • • Provides Odd-HIGH Parity of 12 Inputs Shiftable Output Register with Hold 900ps Max.
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