SEMICONDUCTOR TECHNICAL DATA
Registered Hex PECL/TTL
The MC10H/100H607 is a 6–bit, registered PECL to TTL translator.
The device features differential PECL inputs for both data and clock. The
TTL outputs feature 48mA sink, 24mA source drive capability for driving
high fanout loads or transmission lines. The asynchronous master reset
control is an ECL level input.
With its differential PECL inputs and TTL outputs the H607 device is
ideally suited for the receive function of a HPPI bus type board–to–board
interface application. The on chip registers simplify the task of
synchronizing the data between the two boards.
The device is available in either ECL standard: the 10H device is
compatible with MECL 10H™ logic levels, with a VCC of +5.0 volts, while
the 100H device is compatible with 100K logic levels, with a VCC of +5.0
• Differential ECL Data and Clock Inputs
• 48mA Sink, 15mA Source TTL Outputs
• Single Power Supply
• Multiple Power and Ground Pins to Minimize Noise
Pinout: 28–Lead PLCC (Top View)
Q3 VCCT Q4 TGND Q5 VCCT MR
25 24 23 22 21 20 19
D0 EGND D1
9 10 11
D1 D2 D2
MECL 10H is a trademark of Motorola, Inc.
© Motorola, Inc. 1996