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MC145488 Datasheet Dual Data Link Controller

Manufacturer: Motorola Semiconductor (now NXP Semiconductors)

General Description

and electrical specifications.

It can be ordered from your local Motorola sales office or from the Motorola Literature Distribution Center as MC145488/D.

• Two Independent Full–Duplex Bit–Oriented Protocol Controllers Support HDLC, SDLC, CCITT X.25, CCITT Q.921 (LAPD), and V.120 at Basic and Primary Rates • Four–Channel On–Chip DMA Controller — 64 kbyte Address Range with Expansion Control — Internal Programmable Wait–State Generator — Two Buffer Descriptors for Each Receiver Channel • Compatible with 68000 and 80186 Bus Structures — Non–Multiplexed 16– or 8–Bit Data Bus — Frame Sizes up to 4096 bytes • Bit–Level HDLC Processing Including: — Flag Generation/Detection — Abort Generation/Detection — Zero Insertion/Deletion — CRC–CCITT Generation/Checking — Residue Bit Handler • TEI/SAPI Address Comparison — Three Address

Overview

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary Dual Data Link Controller This technical summary gives a brief overview of the MC145488 Dual Data Link Controller.

The MC145488 is a two–channel ISDN LAPD controller with an on–chip direct memory access (DMA) controller.

It is intended for ISDN terminal and switch applications where one or two channels of data will use HDLC–type protocols.

Key Features

  • and operation of the DDLC. Please refer to the MC145488 DDLC data book for the complete.