MC68341
description on page 3-31: The CPU space decode logic allocates the 256-byte block from $3FF00-3FFFF to the SIM module. An internal 2-clock termination is provided by this initial decode for any access to this range, but selection of specific registers depends on additional decode. Accesses to the MBAR register at long word $3FF00 are internal only, and are only visible by enabling show cycles. Users should directly access only the MBAR register, and use the LPSTOP instruction to generate the LPSTOP broadcast access to $3FFFE. The remaining address range $3FF04-3FFFD is Motorola reserved and should not be accessed.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
© MOTOROLA, 1995
S0 CLKOUT A31- A2
S2
S4
S0
S2
S4
S0
S2
S4
A1 A0 FC3- FC0
SIZ1 WORD SIZ0 BYTE
R/W
CSx DS
AS68K UDS, LDS UWE LWE
DSACK
DTC D15- D8
OP2
OP3
D7- D0 WORD...
