low skew cmos pll clock driver.
* Five Outputs (QO
–Q4) with Output
–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
* The phase varia.
when a central system clock must be distributed synchronously to multiple boards (see Figure 7). Five “Q” outputs (QO
on page 11). A lock indicator output (LOCK) will go high when the loop is in steady
–state phase and frequency lock. The LOCK output will go low if phase
–lock is lost or when the PLL_EN pin is low. Under certain conditi.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 147.04KB)