CYCLE 1 A1
  – A15 tAVWH A0 tA0VWH DCS/TCS (DATA/TAG ENABLE) tWLEH tWLWH WE (WRITE ENABLE) tA0VWL tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH
  .

1MB R4000 Secondary Cache Fast Static RAM Module Set

MCM44256

MCM44256B

MCM4464

MCM44A256B

MCM44A64

MCM44B256B

MCM44B64

MCM44C256B

MCM44C64

MCM44D256B

MCM44D64

MCM44F64

MCM44G64

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