MCM63P531 ram equivalent, 32k x 32 bit pipelined burstram synchronous fast static ram.
Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
MOTOROLA FAST SRAM
MCM63P531 5
WRITE T.
Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overa.
Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle. Synchronous Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (exception — .
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