MCM67M618B Description
It is organized as 65,536 words of 18 bits, fabricated using Motorola’s high performance silicon gate BiCMOS technology. The device integrates input registers, a 2 bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).