The following content is an automatically extracted verbatim text
from the original manufacturer datasheet and is provided for reference purposes only.
View original datasheet text
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MPC2001/D
256KB Asynchronous Secondary Cache Module for PowerPC™
The MPC2001 is designed to provide asynchronous 256KB L2 cache for the PowerPC 60x processors. The module is configured as 32K x 64 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses eight of Motorola’s MCM6206 CMOS RAMs. Eight write enables are provided for byte write control. The cache is designed to interface with the PowerPC 60x bus and requires external tag. PD0 – PD2 are reserved for density and speed identification. The cache is plug and pin compatible with Motorola’s MPC2002 and MPC2003 BurstRAM™ synchronous cache modules.
MPC2001 Datasheet
