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Motorola Electronic Components Datasheet

MTB2N60E Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTB2N60E/D
Designer's Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
G
®
D
S
MTB2N60E
Motorola Preferred Device
TMOS POWER FET
2.0 AMPERES
600 VOLTS
RDS(on) = 3.8 OHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS 600 Vdc
Drain–to–Gate Voltage (RGS = 1.0 M)
VDGR 600 Vdc
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp 10 µs)
ID 2.0 Adc
ID 1.3
IDM 7.0 Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
PD 50 Watts
0.4 W/°C
2.5 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 2.0 Apk, L = 95 mH, RG = 25 )
EAS 190 mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
— Junction to Ambient (1)
RθJC
RθJA
RθJA
2.5 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
©MMoottoororolal,aInTc.M19O9S6 Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB2N60E Datasheet

TMOS POWER FET

No Preview Available !

MTB2N60E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 480 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V(BR)DSS
600
480
Vdc
— mV/°C
IDSS
µAdc
— — 0.25
— — 1.0
IGSS
— — 100 nAdc
VGS(th)
2.0 3.1 4.0 Vdc
— 8.5 — mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 1.0 Adc)
RDS(on) — 3.0 3.8 Ohm
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125°C)
VDS(on)
Vdc
— 8.2
— 8.4
Forward Transconductance (VDS = 50 Vdc, ID = 1.0 Adc)
gFS
1.0 —
— mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
Coss
Crss
— 435 —
— 100 —
— 20 —
pF
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDD = 300 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 18 )
(VDS = 400 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
td(on)
tr
td(off)
tf
QT
Q1
Q2
— 12 — ns
— 21 —
— 30 —
— 24 —
— 13 — nC
— 2.0 —
— 6.0 —
Q3 — 5.0 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
— 1.0 1.6 Vdc
— 0.9 —
Reverse Recovery Time
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
trr ns
— 340 —
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
LD nH
— 3.5 —
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
LS
nH
— 7.5 —
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB2N60E
Description TMOS POWER FET
Maker Motorola
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