MTB50N06VL Datasheet | Motorola Semiconductor

Features of TMOS V - On- resistance Area Product about One- half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology - Faster Switching than E- FET Predecessors Features mon to TMOS V and TMOS E- FETs - Avalanche Energy Specified - IDSS and VDS(on) Specified at Elevated Temperature - Static Parameters are the Same for both TMOS V and TMOS E- FET - Surface Mount Package Available in 16 mm 13- inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain- to- Source Voltage Drain- to- Gate Voltage (RGS = 1.0 MΩ) Gate- to- Source Voltage - Continuous Gate- Source Voltage - Non- Repetitive (tp ≤ 10 ms) Drain Current - Continuous @ 25°C Drain Current - Continuous @ 100°C Drain Current - Single Pulse (tp ≤ 10 µs) Total Power Dissipation @ 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (1) Operating and Storage Temperature Range Single Pulse Drain- to- Source Avalanche Energy - STARTING TJ = 25°C (VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 42 Apk, L = 0.3 m H, RG = 25 Ω) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Ambient (1) ™ Data Sheet V™ Motorola Preferred Device N- Channel Enhancement- Mode Silicon Gate TMOS POWER FET 42 AMPERES 60 VOLTS RDS(on) = 0.032 OHM G S CASE 418B- 02, Style 2 D2PAK Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 ± 15 ± 20 42 30 147 125 0.83 3.0 - 55 to 175 265 1.2 62.5 50 260 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/°C Watts °C m J °C/W TJ, Tstg EAS RθJC RθJA RθJA TL Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds (1) When surface mounted to an FR4 board using the minimum remended pad size. °C Designer’s Data for “Worst Case” Conditions - The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves - representing boundaries on device characteristics - are given to facilitate “worst case”...