MTB55N06Z Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTB55N06Z/D Advance Information TMOS E-FET.™ High Energy Power FET D2PAK for Surface Mount N- Channel Enhancement- Mode Silicon Gate This advanced high voltage TMOS E- FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain- to- source diode with fast recovery time. Designed for high voltage, high speed switching applications in power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. - Avalanche Energy Capability Specified at Elevated Temperature - Source- to- Drain Diode Recovery Time parable to a Discrete Fast Recovery Diode - Low Stored Gate Charge for Efficient Switching - Internal Source- to- Drain Diode Designed to Replace External Zener Transient Suppressor- Absorbs High Energy in the Avalanche Mode - ESD Protected. Designed to Typically Withstand 400 V Machine Model and 4000 V Human Body Model. TMOS POWER FET 55 AMPERES 60 VOLTS RDS(on) = 18 mΩ ™ G CASE 418B- 02, Style 2 D2PAK S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain- to- Source Voltage Drain- to- Gate Voltage (RGS = 1.0 MΩ) Gate- to- Source Voltage - Continuous Gate- to- Source Voltage - Non- Repetitive (tp ≤ 10 ms) Drain Current - Continuous @ TC = 25°C Drain Current - Continuous @ TC = 100°C Drain Current - Single Pulse (tp ≤ 10 µs) Total Power Dissipation @ TC = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (1) Operating and Storage Temperature Range Single Pulse Drain- to- Source Avalanche Energy - Starting TJ = 25°C (VDD = 25 Vdc, VDS = 60 Vdc, VGS = 10 Vdc, Peak IL = 55 Apk, L = 0.3 m H, RG = 25 Ω) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Ambient (1) Maximum...