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XPC855TZP80D4 - (XPC860 Series) Family Hardware Specifications

Features

  • re) with thirty-two 32-bit general-purpose registers (GPRs).
  • The core performs branch prediction with conditional prefetch without conditional execution.
  • 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
  • 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction caches are two-way, set-associative with 128 sets.
  • 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are.

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Datasheet Details

Part number XPC855TZP80D4
Manufacturer Motorola
File Size 942.79 KB
Description (XPC860 Series) Family Hardware Specifications
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Full PDF Text Transcription

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( DataSheet : www.DataSheet4U.com ) Advance Information MPC860EC Rev. 6.3 9/2003 MPC860 Family Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC860 family. This hardware specification covers the following topics: Topic Section 1, “Overview” Section 2, “Features” Section 3, “Maximum Tolerated Ratings” Section 4, “Thermal Characteristics” Section 5, “Power Dissipation” Section 6, “DC Characteristics” Section 7, “Thermal Calculation and Measurement” Section 8, “Layout Practices” Section 9, “Bus Signal Timing” Section 10, “IEEE 1149.
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