DSP56001 Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 24-Bit General Purpose Digital Signal Processor Order this document by DSP56001/D DSP56001 Pin Grid Array (PGA) Available in an 88 pin ceramic through-hole package. Ceramic Quad Flat Pack (CQFP) The DSP56001 is a member of Motorola’s family of Available in a 132 pin, small footprint, HCMOS, low-power, general purpose Digital Signal surface mount package. Processors. The DSP56001 Features 512 words of full speed, on-chip program RAM (PRAM) memory, two Plastic Quad Flat Pack (PQFP) 256 word data RAMs, two preprogrammed data Available in a 132 pin, small footprint, ROMs, and special on-chip bootstrap hardware to persurface mount package. mit convenient loading of user programs into the program RAM. It is an off-the-shelf part since the program memory is user programmable. The core of the processor consists of three execution units operating in parallel - the data ALU, the address generation unit, and the program controller. The DSP56001 has MCU-style on-chip peripherals, program and data memory, as well as a memory expansion port. The MPU-style programming model and instruction set make writing efficient, pact code, straightforward. The high throughput of the DSP56001 makes it well-suited for munication, high-speed control, numeric processing, puter and audio applications. The key Features which facilitate this throughput are: - Speed - Precision - Parallelism At 16.5 million instructions per second (MIPS) with a 33 MHz clock, the DSP56001 can execute a 1024 point plex Fast Fourier Transform in1.98 milliseconds (66,240 clock cycles). The data paths are 24 bits wide thereby providing 144 dB of dynamic range; intermediate results held in the 56-bit accumulators can range over 336 dB. The data ALU, address arithmetic...