D4564163 Datasheet - NEC

UPD4564163

D4564163 Features

* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

* Pulsed interface

* Possible to assert random column address in every cycle

* Quad internal banks controlled by A12 and A13 (Bank Select)

* Byte control (×16) by LDQM and UD

D4564163 General Description

The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. .

D4564163 Datasheet (657.15 KB)

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D4564163

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NEC

File Size:

657.15 KB

Description:

Upd4564163.

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D4564163 Features

D4564163 General Description

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