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  NEC Electronic Components Datasheet  

D720101 Datasheet

UPD720101

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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD720101
USB2.0 HOST CONTROLLER
The µPD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for
high-speed signaling and works up to 480 Mbps. The µPD720101 is integrated 3 host controller cores with PCI
interface and USB2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD720101 User’s Manual: S16336E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host
controller core for high-speed signaling.
• Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
• Configurable number of downstream facing ports (2 to 5)
• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2
• Supports PCI Mobile Design Guide Revision 1.1
• Supports PCI-Bus Power Management Interface Specification release 1.1
• PCI bus bus-master access
• System clock is generated by 30 MHz X’tal or 48 MHz clock input.
System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see µPD720101
User’s Manual.
• Operational registers direct-mapped to PCI memory space
• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number
µPD720101GJ-UEN
µPD720101F1-EA8
Package
144-pin plastic LQFP (Fine pitch) (20 × 20)
144-pin plastic FBGA (12 × 12)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16265EJ4V0DS00 (4th edition)
Date Published June 2004 NS CP (N)
Printed in Japan
The mark shows major revised points.
2002


  NEC Electronic Components Datasheet  

D720101 Datasheet

UPD720101

No Preview Available !

BLOCK DIAGRAM
PCI Bus
PME0
INTA0
INTB0
µPD720101
INTC0
WakeUp_Event
PCI Bus Interface
WakeUp_Event
Arbiter
WakeUp_Event
OHCI
Host
Controller
#1
OHCI
Host
Controller
#2
Root Hub
EHCI
Host
Controller
SMI0
PHY
Port 1
Port 2
Port 3
Port 4
Port 5
USB Bus
Remark INTB0/INTC0 can be shared with INTA0 through BIOS setting. (Planning)
2 Data Sheet S16265EJ4V0DS


Part Number D720101
Description UPD720101
Maker NEC
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D720101 Datasheet PDF






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