UPD16310 Datasheet | NEC

DESCRIPTION µPD16310 is high voltage driver for PDP, EL or VFD graphic panel structured by CMOS process. Logic power supply is 5.0 V connecting direct to control logic. Maximum output voltage is 80 V and maximum current is 50 m A. FEATURES - 80 V Output Voltage Swing Capability - 50 m A Output Sink and Source Current Capability - 40 bit Shift-register and Latch - High Speed Serial DATA Transferring (fmax. = 20 MHz - Low Standby Current 100 µA MIN.) ORDERING INFORMATION Part Number Package 80-pin plastic QFP (3 direction lead) µPD16310GF-3L9 Document No. IC-2859 (1st edition) Date Published March 1997 P Printed in Japan © µPD16310 PIN CONNECTION DIAGRAM (Top View) O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 VDD2 VSS2 VSS2 VSS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 VDD2 VSS2 VSS2 VSS1 R/L VDD1 VDD1 Note The 33 pin (NC) should be open. All the power supply terminals should be used. VSS1 and VSS2 should be respectively connected with themselves outside. To prevent latch up breakdown, the power should be turned ON in order VDD1, logic input, VDD2. It should be turned OFF in the opposite order. This relationship should be followed during transition period as well. µPD16310 BLOCK...