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UPD44325184 - 36M-BIT QDRII SRAM

Download the UPD44325184 datasheet PDF. This datasheet also covers the UPD44325084 variant, as both devices belong to the same 36m-bit qdrii sram family and are provided as variant models within a single manufacturer datasheet.

Description

The µPD44325084 is a 4,194,304-word by 8-bit, the µPD44325094 is a 4,194,304-word by 9-bit, the µPD44325184 is a 2,097,152-word by 18-bit and the µPD44325364 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor me

Features

  • 1.8 ± 0.1 V power supply and HSTL I/O.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Separate independent read and write data ports with concurrent transactions.
  • 100% bus utilization DDR READ and WRITE operation.
  • Four-tick burst for reduced address frequency.
  • Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
  • Two output clocks (C and /C) for precise flight time and clock sk.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UPD44325084_NEC.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number UPD44325184
Manufacturer NEC
File Size 391.77 KB
Description 36M-BIT QDRII SRAM
Datasheet download datasheet UPD44325184 Datasheet

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Other Datasheets by NEC

Part Number Description
UPD44325182 36M-BIT QDRII SRAM
UPD44325082 36M-BIT QDRII SRAM
UPD44325084 36M-BIT QDRII SRAM
UPD44325092 36M-BIT QDRII SRAM
UPD44325094 36M-BIT QDRII SRAM

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD44325084, 44325094, 44325184, 44325364 36M-BIT QDRTMII SRAM 4-WORD BURST OPERATION Description The µPD44325084 is a 4,194,304-word by 8-bit, the µPD44325094 is a 4,194,304-word by 9-bit, the µPD44325184 is a 2,097,152-word by 18-bit and the µPD44325364 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44325084, µPD44325094, µPD44325184 and µPD44325364 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K.
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