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UPD45128841 - 128M-bit Synchronous DRAM 4-bank/ LVTTL

Download the UPD45128841 datasheet PDF. This datasheet also covers the UPD variant, as both devices belong to the same 128m-bit synchronous dram 4-bank/ lvttl family and are provided as variant models within a single manufacturer datasheet.

Description

The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.

Features

  • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge.
  • Pulsed interface.
  • Possible to assert random column address in every cycle.
  • Quad internal banks controlled by BA0(A13) and BA1(A12).
  • Byte control (×16) by LDQM and UDQM.
  • Programmable Wrap sequence (Sequential / Interleave).
  • Programmable burst length (1, 2, 4, 8 and full page).
  • Programmable /CAS latency (2 and 3).
  • Automatic precharge.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UPD-4512.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number UPD45128841
Manufacturer NEC
File Size 1.08 MB
Description 128M-bit Synchronous DRAM 4-bank/ LVTTL
Datasheet download datasheet UPD45128841 Datasheet

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Other Datasheets by NEC

Part Number Description
UPD45128163 128M-bit Synchronous DRAM 4-bank/ LVTTL
UPD45128441 128M-bit Synchronous DRAM 4-bank/ LVTTL
UPD4516161 16M Bit Synchronous DRAM
UPD4516161A 16M Bit Synchronous DRAM
UPD4516421 16M-Bit Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DATA SHEET MOS INTEGRATED CIRCUIT µPD45128441, 45128841, 45128163 128M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin TSOP (II).
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