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UPD23C64202L - 64M-BIT SYNCHRONOUS MASK-PROGRAMMABLE ROM

Description

The µPD23C64202L is a 67,108,864 bits synchronous mask-programmable ROM with multiplexed address bus.

The word organization is selectable (WORD mode : 4,194,304 words by 16 bits, DOUBLE WORD mode : 2,097,152 words by 32 bits).

The µPD23C64202L is packed in 86-pin PLASTIC TSOP (II).

Features

  • Fully synchronous mask-ROM; all signals referenced to a positive clock edge.
  • Word organization : 4,194,304 words by 16 bits (WORD mode) 2,097,152 words by 32 bits (DOUBLE WORD mode).
  • Operation frequency : up to 100 MHz Operation supply voltage VCC Clock frequency MHz Access time from CLK ns (MAX. ) Operating current (Burst mode) mA (MAX. ) 150 Standby current (CMOS level input) µA (MAX. ) 100 5 3.3 V ± 0.3 V 100 83 66 50 33 6 8 9 9 9.
  • Programmable wrap type.

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Datasheet Details

Part number UPD23C64202L
Manufacturer NEC Electronics
File Size 660.44 KB
Description 64M-BIT SYNCHRONOUS MASK-PROGRAMMABLE ROM
Datasheet download datasheet UPD23C64202L Datasheet

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Full PDF Text Transcription

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DATA SHEET µPD23C64202L 64M-BIT SYNCHRONOUS MASK-PROGRAMMABLE ROM 4M-WORD BY 16-BIT (WORD MODE) / 2M-WORD BY 32-BIT (DOUBLE WORD MODE) MOS INTEGRATED CIRCUIT Description The µPD23C64202L is a 67,108,864 bits synchronous mask-programmable ROM with multiplexed address bus. The word organization is selectable (WORD mode : 4,194,304 words by 16 bits, DOUBLE WORD mode : 2,097,152 words by 32 bits). The µPD23C64202L is packed in 86-pin PLASTIC TSOP (II). Features • Fully synchronous mask-ROM; all signals referenced to a positive clock edge • Word organization : 4,194,304 words by 16 bits (WORD mode) 2,097,152 words by 32 bits (DOUBLE WORD mode) • Operation frequency : up to 100 MHz Operation supply voltage VCC Clock frequency MHz Access time from CLK ns (MAX.
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