Description
The S7R643682M, S7R641882M and S7R640982M are 75,497,472-bits Quadruple Synchronous Pipelined Burst SRAMs.
They are organized as 2,097,152 words by 36bits for S7R643682M, 4,194,304 words by 18bits for S7R641882M and 8,388,608 words by 9bits for S7R640982M.
Features
- 1.8V+0.1V/-0.1V Power Supply.
- DLL circuitry for wide output data valid window and future fre-
quency scaling.
- I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/
-0.1V for 1.8V I/O.
- Separate independent read and write data ports
with concurrent read and write operation.
- HSTL I/O.
- Full data coherency, providing most current data.
- Synchronous pipeline read with self timed early write.
- Registered address, control.