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S7T6436U4M Datasheet 2mx36 & 4mx18 & 8mx9 Quadruple-ii+ Bl4 Sram W/ Odt

Manufacturer: NETSOL

Overview: SS77TT66443366UU44MM SS77TT66441188UU44MM SS77TT66440099UU44MM 22MMxx3366&&44MMxx1188&&88MMxx99QQuuaaddrruuppllee--IIII++BBLL44SSRRAAMMww//OODDTT 72Mb Quadruple-II+ BL4 w/ ODT SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of NETSOL. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. For updates or additional information about Netsol products, please contact to netsol@netsol.co.kr Rev. 1.0 Nov. 2013 -1- S7T6436U4M S7T6418U4M S7T6409U4M 2Mx36 & 4Mx18 & 8Mx9 Quadruple-II+ BL4 SRAM w/ ODT Document Title 2Mx36 & 4Mx18 & 8Mx9 - Bit Quadruple-II+ Burst Length of 4 SRAM w/ ODT (2.5 Clock Read Latency) Revision History Rev. No. History 0.0 Initial Draft 1.0 Final spec release Remove θJB parameter in thermal resistance Draft Date Oct. 2012 Nov. 2013 Remark Preliminary Final Rev. 1.0 Nov. 2013 -2- S7T6436U4M S7T6418U4M S7T6409U4M 2Mx36 & 4Mx18 & 8Mx9 Quadruple-II+ BL4 SRAM w/ ODT 2Mx36 & 4Mx18 & 8Mx9 - Bit Quadruple-II+ Burst Length of 4 SRAM w/ ODT (2.

Datasheet Details

Part number S7T6436U4M
Manufacturer NETSOL
File Size 436.75 KB
Description 2Mx36 & 4Mx18 & 8Mx9 Quadruple-II+ BL4 SRAM w/ ODT
Datasheet S7T6436U4M-NETSOL.pdf

Key Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future fre- quency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.
  • Separate independent read and write data ports with concurrent read and write operation.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Read latency: 2.5 clock cycl.

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