* Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to .

The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT16823A has two 9-bit wide buf.

74ABTH16821A

74ABTH16825A

74ABTH16827A

74ABTH16841A

74ABTH16899

74ABTH161543

74ABTH162240

74ABTH162244

74ABTH162245A

74ABTH16240A

74ABTH16241A

74ABTH16244A

74ABTH16245B