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74ABTH16823A Datasheet

18-bit bus interface D-type flip-flop with reset and enable 3-State

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INTEGRATED CIRCUITS
74ABT16823A
74ABTH16823A
18-bit bus interface D-type flip-flop
with reset and enable (3-State)
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

74ABTH16823A Datasheet

18-bit bus interface D-type flip-flop with reset and enable 3-State

No Preview Available !

Philips Semiconductors
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
Product specification
74ABT16823A
74ABTH16823A
FEATURES
Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Live insertion/extraction permitted
Power-up 3-State
74ABTH16823A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Power-up Reset
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
Two options are available, 74ABT16823A which does not have the
bus-hold feature and 74ABTH16823A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
ICCL
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Quiescent supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
VO = 0V or VCC; 3-State
Outputs disabled; VCC = 5.5V
Outputs low; VCC = 5.5V
TYPICAL
2.3
1.9
4
6
500
9
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT16823A DL
–40°C to +85°C
74ABT16823A DGG
–40°C to +85°C
74ABTH16823A DL
–40°C to +85°C
74ABTH16823A DGG
NORTH AMERICA
BT16823A DL
BT16823A DGG
BH16823A DL
BH16823A DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
2, 27
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
56, 29
55, 30
1, 28
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
1998 Feb 27
SYMBOL
1OE, 2OE
1D0-1D8
2D0-2D8
1Q0-1Q8
2Q0-2Q8
1CP, 2CP
1CE, 2CE
1MR, 2MR
GND
VCC
2
FUNCTION
Output enable input (active-Low)
Data inputs
Data outputs
Clock pulse input (active rising edge)
Clock enable input (active-Low)
Master reset input (active-Low)
Ground (0V)
Positive supply voltage
853-1791 19025


Part Number 74ABTH16823A
Description 18-bit bus interface D-type flip-flop with reset and enable 3-State
Maker NXP
Total Page 12 Pages
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