74AHC02
FEATURES
- ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Inputs accepts voltages higher than VCC
- For AHC only: operates with CMOS input levels
- For AHCT only: operates with TTL input levels
- Specified from
- 40 to +85 and +125 °C. DESCRIPTION
The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the Quad 2-input OR function. FUNCTION TABLE See note 1. INPUT n A L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. n B L H L H OUTPUT n Y H L L L QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
74AHC02; 74AHCT02
TYPICAL SYMBOL t PHL/t PLH CI CO CPD PARAMETER propagation delay n A, n B to n Y input capacitance output capacitance power dissipation capacitance CL = 50 p F; f = 1 MHz;...
