74ALS109A Datasheet | NXP Semiconductors

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and plementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation. TYPICAL SUPPLY CURRENT (TOTAL) 3.0m A PIN CONFIGURATION RD0 J0 K0 CP0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD1 J1 K1 CP1 SD1 Q1 Q1 SF00135 TYPE 74ALS109A TYPICAL f MAX 150MHz ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS109AN 74ALS109AD DRAWING NUMBER SOT38-4 SOT109-1 16-pin plastic DIP 16-pin plastic SO INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS J0, J1 K0, K1 CP0, CP1 SD0, SD1 RD0, RD1 Q0, Q1, Q0, Q1 J inputs K inputs Clock inputs (active rising edge) Set inputs (active-Low) Reset inputs (active-Low) Data outputs DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/2.0 1.0/2.0 1.0/2.0 1.0/4.0 1.0/4.0 20/80 LOAD VALUE HIGH/LOW 20µA/0.2m A 20µA/0.2m A 20µA/0.2m A 20µA/0.4m A 20µA/0.4m A 0.4m A/8m A NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1m A in the Low state. LOGIC SYMBOL 2 14 3 13 IEC/IEEE SYMBOL 2 4 6 1J C1 1K R S 4 5 1 12 11 15 CP0 SD0 RD0 CP1 SD1 RD1 J0 J1 K0 K1 3 1 5 14 Q0 Q0 Q1 Q1 12 13 15 6 7 10 9 11 2J C2 2K R...