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74ALS174 - Hex D flip-flop

General Description

The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered.

Key Features

  • Four edge-triggered D flip-flops.
  • Buffered common clock.
  • Buffered asynchronous master reset.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74ALS174 Hex D flip–flop Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification Hex D flip-flop 74ALS174 FEATURES • Four edge-triggered D flip-flops • Buffered common clock • Buffered asynchronous master reset DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.