74ALVC162836A Datasheet | NXP Semiconductors

URES - Wide supply voltage range of 1.2 V to 3.6 V - plies with JEDEC standard no. 8-1A. - CMOS low power consumption - Direct interface with TTL levels - Current drive ± 12 m A at 3.0 V - MULTIBYTETM flow-through standard pin-out architecture - Low inductance multiple VCC and GND pins for minimum noise and ground bounce PIN CONFIGURATION OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6 Y7 GND Y8 Y9 Y10 Y11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CP A1 A2 GND A3 A4 VCC A5 A6 A7 GND A8 A9 A10 A11 A12 A13 GND A14 A15 A16 VCC A17 A18 GND A19 A20 LE - Output drive capability 50 Ω transmission lines @ 85°C - Integrated 30 W termination resistors - Diode clamps to VCC and GND on all inputs - Input diodes to acmodate strong drivers DESCRIPTION The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop. The 74ALVC162836A is designed with 30 W_series resistors in both HIGH or LOW output stages. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip -flop. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Y12 Y13 GND Y14 Y15 Y16 VCC Y17 Y18 GND Y19 Y20 NC SH00197 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5ns SYMBOL t PHL/t PLH fmax CI CI/O PARAMETER Propagation delay An to Yn; LE to Yn; CP to Yn Maximum clock frequency Input capacitance Input/Output capacitance transparent mode Output enabled Output...