Datasheet4U Logo Datasheet4U.com

74ALVT16823 - 18-bit bus-interface D-type flip-flop

Datasheet Summary

Description

The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

Features

  • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops.

📥 Download Datasheet

Datasheet preview – 74ALVT16823

Datasheet Details

Part number 74ALVT16823
Manufacturer NXP
File Size 99.78 KB
Description 18-bit bus-interface D-type flip-flop
Datasheet download datasheet 74ALVT16823 Datasheet
Additional preview pages of the 74ALVT16823 datasheet.

📁 Similar Datasheet

  • 74ALVT16823 - 18-bit bus-interface D-type flip-flop (nexperia)
  • 74ALVT16821 - 20-bit bus interface D-type flip-flop (nexperia)
  • 74ALVT16827 - 20-bit buffer/line driver (nexperia)
  • 74ALVT162245 - 16-bit transceiver (nexperia)
  • 74ALVT16240 - 16-bit inverting buffer/driver (NXP Semiconductors)
  • 74ALVT16244 - 16-bit buffer/line driver (nexperia)
  • 74ALVT162821 - 20-bit bus interface D-type flip-flop (nexperia)
  • 74ALVT162823 - 18-bit bus-interface D-type flip-flop (Philips)
  • 74ALVT162823 - 18-bit bus-interface D-type flip-flop (nexperia)
  • 74ALVT162827 - 20-bit buffer/line driver (nexperia)
Other Datasheets by NXP

Full PDF Text Transcription

Click to expand full text
INTEGRATED CIRCUITS 74ALVT16823 18-bit bus-interface D-type flip-flop with reset and enable (3-State) Product specification Supersedes data of 1998 Mar 03 IC23 Data Handbook 1998 Jun 12 Philips Semiconductors Philips Semiconductors Product specification 2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ALVT16823 FEATURES • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.
Published: |