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74AUP1G14 Datasheet

Low-power Schmitt-trigger inverter

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74AUP1G14
Low-power Schmitt-trigger inverter
Rev. 01 — 20 July 2005
Product data sheet
1. General description
The 74AUP1G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G14 provides a single inverting Schmitt-trigger which accepts standard input
signals. It is capable of transforming slowly changing input signals into sharply defined,
jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V(th)LH and the negative voltage V(th)HL is defined as the input
hysteresis voltage Vhys.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s ESD protection:
x HBM JESD22-A114-C exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C
3. Applications
s Wave and pulse shaper
s Astable multivibrator
s Monostable multivibrator


NXP Semiconductors Electronic Components Datasheet

74AUP1G14 Datasheet

Low-power Schmitt-trigger inverter

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Philips Semiconductors
74AUP1G14
Low-power Schmitt-trigger inverter
4. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf 3 ns.
Symbol Parameter
Conditions
tPHL, tPLH propagation delay
A to Y
CL = 5 pF; RL = 1 M;
VCC = 0.8 V
CL = 5 pF; RL = 1 M;
VCC = 1.1 V to 1.3 V
CL = 5 pF; RL = 1 MΩ;
VCC = 1.4 V to 1.6 V
CL = 5 pF; RL = 1 M;
VCC = 1.65 V to 1.95 V
CL = 5 pF; RL = 1 M;
VCC = 2.3 V to 2.7 V
CL = 5 pF; RL = 1 M;
VCC = 3.0 V to 3.6 V
Ci input capacitance
CPD power dissipation VCC = 1.8 V; f = 10 MHz
capacitance
VCC = 3.3 V; f = 10 MHz
Min
-
3.0
2.6
2.2
2.0
1.9
-
[1] [2] -
[1] [2] -
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC.
5. Ordering information
Typ Max Unit
20.3 -
ns
5.9 11.7 ns
4.3 7.6 ns
3.7 6.2 ns
3.1 4.8 ns
2.8 4.0 ns
0.8 -
4.6 -
6.1 -
pF
pF
pF
Table 2: Ordering information
Type number
Package
Temperature range Name
74AUP1G14GW 40 °C to +125 °C TSSOP5
74AUP1G14GM 40 °C to +125 °C XSON6
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
6. Marking
Table 3: Marking
Type number
74AUP1G14GW
74AUP1G14GM
Marking code
pF
pF
9397 750 14676
Product data sheet
Rev. 01 — 20 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2 of 20


Part Number 74AUP1G14
Description Low-power Schmitt-trigger inverter
Maker NXP
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